1. Field of the Invention
The present invention relates to user-programmable antifuse technology. More particularly, the present invention relates to metal-to-metal antifuses and to above-via metal-to-metal antifuses.
2. The Prior Art
In the practice of antifuse fabrication technology, it has been found that scaling problems occur when depositing antifuse material, such as PECVD amorphous silicon, into via openings having depths greater than about 0.4 microns and widths narrower than about 1.0 microns. These scaling problems consist of reduced antifuse breakdown voltage and uniformity and increased current leakage in the antifuse structure. As the depth/width aspect ratio of the antifuse via increases, the scaling problems get worse. This is due to the reduced step coverage (final thickness) of the antifuse material at the bottom of the antifuse via. As the antifuse via depth increases and or the width gets smaller, step coverage of most deposited films gets worse and the scaling problems increase. If the antifuse material layer is thickened to obtain higher breakdown voltage, a problem develops with the top electrode. Because the via is even smaller after the antifuse material layer is deposited, it becomes very hard to deposit enough upper electrode material into the via to ensure it will be reliable.
For example, if about 1,000 angstroms of amorphous silicon antifuse material (for a 10 volt antifuse breakdown voltage value) is required in the bottom of the via and the step coverage into a via having an initial size of 0.8 microns is 60%, the amorphous silicon deposition thickness required will be 0.18, so the sidewall coverage of the via at its thickest point at the top of the via will be about 0.18 microns. The resulting reduced-size via available for metal deposition is then roughly 0.8-0.36=0.44 microns wide. When depositing the top metal electrode into this 0.44 micron wide via, the amount of metal which can be deposited is limited by the fact that the via tends to close off during the deposition process, leaving a partial void. If the via is 0.44 microns, only 0.22 microns of metal may be deposited on the via sides before the via closes off. At about 50% step coverage inside the via, the 0.22 microns/side top electrode metal is about 0.11 microns thick at its thinnest point on the sidewall of the via. Because the via is now closed off, there is no room left for any interconnect metal to get into the via and the reliability of about 0.11 microns of top electrode as an interconnect may be a concern.
As those of ordinary skill in the art will appreciate, when this process is scaled to a via of 0.6 microns, and 0.2 microns/side of amorphous silicon is deposited (0.2 microns at 50% step coverage=0.1 microns at the bottom of the via, a reduced step coverage as via gets smaller) there is only 0.6-0.4=0.2 microns via left into which to deposit the top electrode. Now only 0.1 micron/side of top electrode can be deposited before the via closes off and, at 40% step coverage (step coverage is less due to smaller via size), there will be about 400angstroms of top electrode as metal interconnect to the antifuse material at the thinnest point on the via sidewall. This 400 angstroms of interconnection to the antifuse in the via is a big reliability concern.